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ICS9DB803DI idt tm /ics tm eight output differential buffer for pcie gen 2 ICS9DB803DI rev a 06/18/08 eight output differential buffer for pcie gen 2 datasheet 1 stop logic src_in src_in# dif(7:0)) control logic bypass#/pll s data sclk pd# spread compatible pll 8 iref oe_(7:0) 8 lock src_stop# high_bw# m u x description output features the 9db803 is a db800 version 2.0 yellow cover part with pci express gen ii support. it can be used in pc or embedded systems to provide outputs that have low cycle-to-cycle jitter (50ps), low output-to-output skew (100ps), and are pci express gen 2 compliant. the 9db803 supports a 1 to 8 output configuration, taking a spread or non spread differential hcsl input from a ck410(b) main clock such as 954101 and 932s401, or any other differential hcsl pair. 9db803 can generate hcsl or lvds outputs from 50 to 100mhz in pll mode or 50 to 400mhz in bypass mode. there are two de- jittering modes available selectable through the high_bw# input pin, high bandwidth mode provides de-jittering for spread inputs and low bandwidth mode provides extra de-jittering for non-spread inputs. the src_in#, pd#, and individual oe real- time input pins provide completely programmable power management control. ? 8 - 0.7v current-mode differential output pairs supports zero delay buffer mode and fanout mode bandwidth programming available funtional block diagram key specifications outputs cycle-cycle jitter < 50ps outputs skew: 50ps 50-100 mhz operation in pll mode 50-400 mhz operation in bypass mode phase jitter: pcie gen1 < 86ps peak to peak phase jitter: pcie gen2 < 3.1ps rms 48-pin ssop/tssop package available in rohs compliant packaging features/benefits spread spectrum modulation tolerant, 0 to -0.5% down spread and +/- 0.25% center spread. supports undriven differential outputs in pd# and src_stop# modes for power management. note: polarities shown for oe_inv = 0.
idt tm /ics tm eight output differential buffer for pcie gen 2 ICS9DB803DI rev a 06/18/08 ICS9DB803DI eight output differential buffer for pcie for gen 2 2 pin configuration polarity inversion pin list table src_div# 1 48 vdda vdd 2 47 gnda gnd 3 46 iref src_in 4 45 lock src_in# 5 44 oe_7 oe_0 6 43 oe_4 oe_3 7 42 dif_7 dif_0 8 41 dif_7# dif_0# 9 40 oe_inv gnd 10 39 vdd vdd 11 38 dif_6 dif_1 12 37 dif_6# dif_1# 13 36 oe_6 oe_1 14 35 oe_5 oe_2 15 34 dif_5 dif_2 16 33 dif_5# dif_2# 17 32 gnd gnd 18 31 vdd vdd 19 30 dif_4 dif_3 20 29 dif_4# dif_3# 21 28 high_bw# bypass#/pll 22 27 dif_stop# sclk 23 26 pd# sdata 24 25 gnd oe_inv = 0 ics9db803 (same as ics9db108) src_div# 1 48 vdda vdd 2 47 gnda gnd 3 46 iref src_in 4 45 lock src_in# 5 44 oe7# oe0# 643 oe4# oe3# 742dif_7 dif_0 8 41 dif_7# dif_0# 9 40 oe_inv gnd 10 39 vdd vdd 11 38 dif_6 dif_1 12 37 dif_6# dif_1# 13 36 oe6# oe1# 14 35 oe5# oe2# 15 34 dif_5 dif_2 16 33 dif_5# dif_2# 17 32 gnd gnd 18 31 vdd vdd 19 30 dif_4 dif_3 20 29 dif_4# dif_3# 21 28 high_bw# bypass#/pll 22 27 dif_stop sclk 23 26 pd sdata 24 25 gnd oe_inv = 1 ics9db803 (same as ics9db801) 01 6oe_0 oe0# 7oe_3 oe3# 14 oe_1 oe1# 15 oe_2 oe2# 26 pd# pd 27 dif_stop# dif_stop 35 oe_5 oe5# 36 oe_6 oe6# 43 oe_4 oe4# 44 oe_7 oe7# pins oe_inv vdd gnd 2 3 src_in/src_in# 6,11,19, 31,39 10,18, 25,32 dif(7:0) n/a 47 iref 48 47 analog vdd & gnd for pll core description pin number power groups
idt tm /ics tm eight output differential buffer for pcie gen 2 ICS9DB803DI rev a 06/18/08 ICS9DB803DI eight output differential buffer for pcie for gen 2 3 pin description for oe_inv = 0 pin # pin name pin type description 1src_div# in active low input for determining src output frequency src or src/2. 0 = src/2, 1= src 2 vdd pwr power supply, nominal 3.3v 3 gnd pwr ground pin. 4 src_in in 0.7 v differential src true input 5 src_in# in 0.7 v differential src complementary input 6oe_0 in active high input for enabling output 0. 0 = tri-state outputs, 1= enable outputs 7oe_3 in active high input for enabling output 3. 0 = tri-state outputs, 1= enable outputs 8 dif_0 out 0.7v differential true clock output 9 dif_0# out 0.7v differential complement clock output 10 gnd pwr ground pin. 11 vdd pwr power supply, nominal 3.3v 12 dif_1 out 0.7v differential true clock output 13 dif_1# out 0.7v differential complement clock output 14 oe_1 in active high input for enabling output 1. 0 = tri-state outputs, 1= enable outputs 15 oe_2 in active high input for enabling output 2. 0 = tri-state outputs, 1= enable outputs 16 dif_2 out 0.7v differential true clock output 17 dif_2# out 0.7v differential complement clock output 18 gnd pwr ground pin. 19 vdd pwr power supply, nominal 3.3v 20 dif_3 out 0.7v differential true clock output 21 dif_3# out 0.7v differential complement clock output 22 bypass#/pll in input to select bypass(fan-out) or pll (zdb) mode 0 = bypass mode, 1= pll mode 23 sclk in clock pin of smbus circuitry, 5v tolerant. 24 sdata i/o data pin for smbus circuitry, 5v tolerant.
idt tm /ics tm eight output differential buffer for pcie gen 2 ICS9DB803DI rev a 06/18/08 ICS9DB803DI eight output differential buffer for pcie for gen 2 4 pin description for oe_inv = 0 pin # pin name pin type description 25 gnd pwr ground pin. 26 pd# in asynchronous active low input pin used to power down the device. the internal clocks are disabled and the vco and the crystal are stopped. 27 dif_stop# in active low input to stop differential output clocks. 28 high_bw# pwr 3.3v input for selecting pll band width 0 = high, 1= low 29 dif_4# out 0.7v differential complement clock output 30 dif_4 out 0.7v differential true clock output 31 vdd pwr power supply, nominal 3.3v 32 gnd pwr ground pin. 33 dif_5# out 0.7v differential complement clock output 34 dif_5 out 0.7v differential true clock output 35 oe_5 in active high input for enabling output 5. 0 = tri-state outputs, 1= enable outputs 36 oe_6 in active high input for enabling output 6. 0 = tri-state outputs, 1= enable outputs 37 dif_6# out 0.7v differential complement clock output 38 dif_6 out 0.7v differential true clock output 39 vdd pwr power supply, nominal 3.3v 40 oe_inv in this latched input selects the polarity of the oe pins. 0 = oe pins active high, 1 = oe pins active low (oe#) 41 dif_7# out 0.7v differential complement clock output 42 dif_7 out 0.7v differential true clock output 43 oe_4 in active high input for enabling output 4. 0 = tri-state outputs, 1= enable outputs 44 oe_7 in active high input for enabling output 7. 0 = tri-state outputs, 1= enable outputs 45 lock out 3.3v output indicating pll lock status. this pin goes high when lock is achieved. 46 iref in this pin establishes the reference current for the differential current- mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 47 gnda pwr ground pin for the pll core. 48 vdda pwr 3.3v power for the pll core.
idt tm /ics tm eight output differential buffer for pcie gen 2 ICS9DB803DI rev a 06/18/08 ICS9DB803DI eight output differential buffer for pcie for gen 2 5 pin description for oe_inv = 1 pin # pin name pin type description 1src_div# in active low input for determining src output frequency src or src/2. 0 = src/2, 1= src 2 vdd pwr power supply, nominal 3.3v 3 gnd pwr ground pin. 4 src_in in 0.7 v differential src true input 5 src_in# in 0.7 v differential src complementary input 6oe0# in active low input for enabling dif pair 0. 1 = tri-state outputs, 0 = enable outputs 7oe3# in active low input for enabling dif pair 3. 1 = tri-state outputs, 0 = enable outputs 8 dif_0 out 0.7v differential true clock output 9 dif_0# out 0.7v differential complement clock output 10 gnd pwr ground pin. 11 vdd pwr power supply, nominal 3.3v 12 dif_1 out 0.7v differential true clock output 13 dif_1# out 0.7v differential complement clock output 14 oe1# in active low input for enabling dif pair 1. 1 = tri-state outputs, 0 = enable outputs 15 oe2# in active low input for enabling dif pair 2. 1 = tri-state outputs, 0 = enable outputs 16 dif_2 out 0.7v differential true clock output 17 dif_2# out 0.7v differential complement clock output 18 gnd pwr ground pin. 19 vdd pwr power supply, nominal 3.3v 20 dif_3 out 0.7v differential true clock output 21 dif_3# out 0.7v differential complement clock output 22 bypass#/pll in input to select bypass(fan-out) or pll (zdb) mode 0 = bypass mode, 1= pll mode 23 sclk in clock pin of smbus circuitry, 5v tolerant. 24 sdata i/o data pin for smbus circuitry, 5v tolerant.
idt tm /ics tm eight output differential buffer for pcie gen 2 ICS9DB803DI rev a 06/18/08 ICS9DB803DI eight output differential buffer for pcie for gen 2 6 pin description for oe_inv = 1 pin # pin name pin type description 25 gnd pwr ground pin. 26 pd in asynchronous active high input pin used to power down the device. the internal clocks are disabled and the vco is stopped. 27 dif_stop in active high input to stop differential output clocks. 28 high_bw# pwr 3.3v input for selecting pll band width 0 = high, 1= low 29 dif_4# out 0.7v differential complement clock output 30 dif_4 out 0.7v differential true clock output 31 vdd pwr power supply, nominal 3.3v 32 gnd pwr ground pin. 33 dif_5# out 0.7v differential complement clock output 34 dif_5 out 0.7v differential true clock output 35 oe5# in active low input for enabling dif pair 5. 1 = tri-state outputs, 0 = enable outputs 36 oe6# in active low input for enabling dif pair 6. 1 = tri-state outputs, 0 = enable outputs 37 dif_6# out 0.7v differential complement clock output 38 dif_6 out 0.7v differential true clock output 39 vdd pwr power supply, nominal 3.3v 40 oe_inv in this latched input selects the polarity of the oe pins. 0 = oe pins active high, 1 = oe pins active low (oe#) 41 dif_7# out 0.7v differential complement clock output 42 dif_7 out 0.7v differential true clock output 43 oe4# in active low input for enabling dif pair 4 1 = tri-state outputs, 0 = enable outputs 44 oe7# in active low input for enabling dif pair 7. 1 = tri-state outputs, 0 = enable outputs 45 lock out 3.3v output indicating pll lock status. this pin goes high when lock is achieved. 46 iref in this pin establishes the reference current for the differential current- mode output pairs. this pin requires a fixed precision resistor tied to ground in order to establish the appropriate current. 475 ohms is the standard value. 47 gnda pwr ground pin for the pll core. 48 vdda pwr 3.3v power for the pll core.
idt tm /ics tm eight output differential buffer for pcie gen 2 ICS9DB803DI rev a 06/18/08 ICS9DB803DI eight output differential buffer for pcie for gen 2 7 absolute max electrical characteristics - input/supply/common output parameters t a = -40 - 85c; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage v ih 3.3 v +/-5% 2 v dd + 0.3 v input low voltage v il 3.3 v +/-5% gnd - 0.3 0.8 v input high current i ih v in = v d d -5 5 ua i il1 v in = 0 v; inputs with no pull-up resistors -5 ua i il2 v in = 0 v; inputs with pull-up resistors -200 ua operating supply current i dd3. 3op full active, c l = full load; 200 ma all diff pairs driven 60 ma all differential pairs tri-stated 6 ma f ipll pll mode 50 110 mhz 1 f ibypass bypass mode 50 400 mhz 1 pin inductance l p in 7nh1 c in logic inputs 1.5 5 pf 1 c out output pin capacitance 6 pf 1 pll bandwidth when pll_bw=0 2 3 4 mhz 1 pll bandwidth when pll_bw=1 0.7 1 1.4 mhz 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 1ms1,2 modulation frequency f mo d triangular modulation 30 33 khz 1 tdrive_src_stop# t drvstp dif output enable after src_stop# de-assertion 10 ns 1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 300 us 1,3 tfall t f fall time of pd# and src_stop# 5 ns 1 trise t r rise time of pd# and src_stop# 5 ns 2 1 guaranteed by design and characterization, not 100% tested in production. 2 see timing diagrams for timing requirements. i dd3. 3pd 3 time from deassertion until out p uts are >200 mv capacitance input low current powerdown current pll bandwidth bw input frequency symbol parameter min max units vdd_a 3.3v core supply voltage 4.6 v vdd_in 3.3v logic supply voltage 4.6 v v il input low voltage gnd-0.5 v v ih input high voltage v d d +0.5v v ts storage temperature -65 150 c tambient ambient operating temp -40 85 c tcase case temperature 115 c esd prot input esd protection human body model 2000 v
idt tm /ics tm eight output differential buffer for pcie gen 2 ICS9DB803DI rev a 06/18/08 ICS9DB803DI eight output differential buffer for pcie for gen 2 8 electrical characteristics - clock input parameters t a = -40 - 85c; supply voltage v dd = 3.3 v +/-5% parameter symbol conditions min typ max units notes input high voltage - dif_in v i hdi f differential inputs (single-ended measurement) 600 800 1150 mv 1 input low voltage - dif_in v ildif differential inputs (single-ended measurement) v ss - 300 0 300 mv 1 input common mode voltage - dif_in v com common mode input voltage 300 1000 mv 1 input amplitude - dif_in v swing peak to peak value 300 1450 mv 1 input slew rate - dif_in dv/dt measured differentially 0.4 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua 1 input duty cycle d tin measurement from differential wavefrom 45 55 % 1 input jitter - cycle to cycle j difin differential measurement 0 125 ps 1 1 guaranteed by design and characterization, not 100% tested in production. 2 slew rate measured through vswing min centered around differential zero
idt tm /ics tm eight output differential buffer for pcie gen 2 ICS9DB803DI rev a 06/18/08 ICS9DB803DI eight output differential buffer for pcie for gen 2 9 electrical characteristics - dif 0.7v current mode differential pair t a = -40 - 85c; v dd = 3.3 v +/-5%; c l =2pf, r s =33.2 ? , r p =49.9 ? , r ref =475 ? parameter symbol conditions min typ max units notes current source output im p edance zo 1 v o = v x 3000 ? 1 volta g e hi g hvhi g h 660 850 1,3 volta g e low vlow -150 150 1,3 max volta g evovs 1150 1 min volta g e vuds -300 1 crossin g volta g e ( abs ) vcross ( abs ) 250 550 mv 1 crossin g volta g e ( var ) d-vcross variation of crossin g over all ed g es 140 mv 1 lon g accurac y pp msee t p eriod min-max values 0 pp m1,2 rise time t r v ol = 0.175v, v oh = 0.525v 175 700 ps 1 fall time t f v oh = 0.525v v ol = 0.175v 175 700 ps 1 rise time variation d-t r 125 ps 1 fall time variation d-t f 125 ps 1 duty cycle d t3 measurement from differential wavefrom 45 50 55 % 1 skew t sk3 v t = 50% 60 ps 1 pll mode 40 50 p s1,5 bypass mode as additive j itter 15 50 p s1,5 pcie gen 1 specs (p k to p k value ) 30 86 ps 1,6,7 pcie gen 2 specs ( rms value ) 2.6 3.1 ps 1,6,7 pcie gen 1 specs (p k to p k value ) 40 86 ps 1,6,7 pcie gen 2 specs ( rms value ) 2.8 3.1 ps 1,6,7 1 guaranteed b y desi g n and characterization, not 100% tested in p roduction. 3 i ref = v dd / (3xr r ). for r r = 475 ? (1%), i ref = 2.32ma. i oh = 6 x i ref and v oh = 0.7v @ z o =50 ? . 4 a pp lies to b yp ass mode onl y 5 measured from differential waveform 6 see htt p ://www. p cisi g .com for com p lete s p ecs 7 device driven b y hp81134a pulse generator 2 all long term accuracy specifications are guaranteed with the a ssumption that the input clock complies with ck409/ck410/ck505 accuracy requirements. the 9db403/803 it self does not contribute to ppm error. t jphasepll jitter, cycle to cycle t jcyc-cyc t jphasebypass jitter, phase statistical measurement on single ended signal using oscilloscope math function. mv measurement on single ended signal using absolute value. mv
idt tm /ics tm eight output differential buffer for pcie gen 2 ICS9DB803DI rev a 06/18/08 ICS9DB803DI eight output differential buffer for pcie for gen 2 10 clock periods differential outputs with spread spectrum enabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock lg- -ssc -ppm error 0ppm + ppm error +ssc lg+ absolute period short-term avera g e long-term avera g e period long-term avera g e short-term avera g e period minimum absolute period minimum absolute period minimum absolute period nominal maximum maximum maximum dif 100 9.87400 9.99900 9.99900 10.00000 10.00100 10.05130 10.17630 ns 1,2,3 dif 133 7.41425 7.49925 7.49925 7.50000 7.50075 7.53845 7.62345 ns 1,2,4 dif 166 5.91440 5.99940 5.99940 6.00000 6.00060 6.03076 6.11576 ns 1,2,4 dif 200 4.91450 4.99950 4.99950 5.00000 5.00050 5.02563 5.11063 ns 1,2,4 dif 266 3.66463 3.74963 3.74963 3.75000 3.75038 3.76922 3.85422 ns 1,2,4 dif 333 2.91470 2.99970 2.99970 3.00000 3.00030 3.01538 3.10038 ns 1,2,4 dif 400 2.41475 2.49975 2.49975 2.50000 2.50025 2.51282 2.59782 ns 1,2,4 clock periods differential outputs with spread spectrum disabled 1 clock 1us 0.1s 0.1s 0.1s 1us 1 clock lg- -ssc -ppm error 0ppm + ppm error +ssc lg+ absolute period short-term avera g e long-term avera g e period long-term avera g e short-term avera g e period minimum absolute period minimum absolute period minimum absolute period nominal maximum maximum maximum dif 100 9.87400 9.99900 10.00000 10.00100 10.17630 ns 1,2,3 dif 133 7.41425 7.49925 7.50000 7.50075 7.62345 ns 1,2,4 dif 166 5.91440 5.99940 6.00000 6.00060 6.11576 ns 1,2,4 dif 200 4.91450 4.99950 5.00000 5.00050 5.11063 ns 1,2,4 dif 266 3.66463 3.74963 3.75000 3.75038 3.85422 ns 1,2,4 dif 333 2.91470 2.99970 3.00000 3.00030 3.10038 ns 1,2,4 dif 400 2.41475 2.49975 2.50000 2.50025 2.59782 ns 1,2,4 1 guaranteed by design and characterization, not 100% tested in production. 3 driven by src output of main clock, pll or bypass mode 4 driven by cpu output of ck410/ck505 main clock, b yp ass mode onl y definition units signal name signal name measurement window symbol 2 all long term accuracy specifications are guaranteed with the assumption that the input clock complies with ck409/ck410/ck505 accuracy requirements. the 9db403/803 itself does not contribute to ppm error. notes notes definition measurement window units symbol
idt tm /ics tm eight output differential buffer for pcie gen 2 ICS9DB803DI rev a 06/18/08 ICS9DB803DI eight output differential buffer for pcie for gen 2 11 src reference clock common recommendations for differential routing dimension or value unit figure l1 length, route as non-coupled 50 ohm trace. 0.5 max inch 1 l2 length, route as non-coupled 50 ohm trace. 0.2 max inch 1 l3 length, route as non-coupled 50 ohm trace. 0.2 max inch 1 rs 33 ohm 1 rt 49.9 ohm 1 down device differential routing dimension or value unit figure l4 length, route as coupled microstrip 100 ohm differential trace. 2 min to 16 max inch 1 l4 length, route as coupled stripline 100 ohm differential trace. 1.8 min to 14.4 max inch 1 differential routing to pci express connector dimension or value unit figure l4 length, route as coupled microstrip 100 ohm differential trace. 0.25 to 14 max inch 2 l4 length, route as coupled stripline 100 ohm differential trace. 0.225 min to 12.6 max inch 2 figure 1 down device routing. rs rs rt rt hscl output buffer pci ex board down device ref_clk input l1 l2 l3? l4 l1? l2? l3 l4? figure 1 figure 2 pci express connector routing. rs rs rt rt hscl output buffer pci ex add in board ref_clk input l1 l2 l3? l4 l1? l2? l3 l4? figure 2
idt tm /ics tm eight output differential buffer for pcie gen 2 ICS9DB803DI rev a 06/18/08 ICS9DB803DI eight output differential buffer for pcie for gen 2 12 alternative termination for lvds and other common differential signals. figure 3. vdiff vp-p vcm r1 r2 r3 r4 note 0.45 v 0.22v 1.08 33 150 100 100 0.58 0.28 0.3 0.6 33 78.7 137 100 0.80 0.40 0.6 33 78.7 none 100 ics874003i-02 input compatible 0.60 1.2 33 174 140 100 standard lvds r1a = r1b = r1 r2a = r2b = r2 cable connected ac coupled application, figure 4 component value note r5a,r5b 5% r6a,r6b cc 0.1 0.350 vcm volts figure_3. r1b r1a r2a r2b hscl output buffer down device ref_clk input l1 l2 l3? l4 l1? l2? l3 l4? r3 r4 figure_4. pcie device ref_clk input l4 l4? r6b r5b r6a r5a 3.3 volts cc cc 8.2k 5% uf 1k
idt tm /ics tm eight output differential buffer for pcie gen 2 ICS9DB803DI rev a 06/18/08 ICS9DB803DI eight output differential buffer for pcie for gen 2 13 general smbus serial interface information for the ICS9DB803DI how to write: ? controller (host) sends a start bit. controller (host) sends the write address dc (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) sends the data byte count = x ics clock will acknowledge controller (host) starts sending byte n through byte n + x -1 ics clock will acknowledge each byte one at a time controller (host) sends a stop bit how to read: controller (host) will send start bit. controller (host) sends the write address dc (h) ics clock will acknowledge controller (host) sends the begining byte location = n ics clock will acknowledge controller (host) will send a separate start bit. controller (host) sends the read address dd (h) ics clock will acknowledge ics clock will send the data byte count = x ics clock sends byte n + x -1 ics clock sends byte 0 through byte x (if x (h) was written to byte 8) . controller (host) will need to acknowledge each byte controllor (host) will send a not acknowledge bit controller (host) will send a stop bit ics (slave/receiver) t wr ack ack ack ack ack pstop bit x byte index block write operation slave address dc (h) beginning byte = n write start bit controller (host) byte n + x - 1 data byte count = x beginning byte n t start bit wr write rt repeat start rd read beginning byte n byte n + x - 1 n not acknowledge pstop bit slave address dd (h) index block read operation slave address dc (h) beginning byte = n ack ack data byte count = x ack ics (slave/receiver) controller (host) x byte ack ack
idt tm /ics tm eight output differential buffer for pcie gen 2 ICS9DB803DI rev a 06/18/08 ICS9DB803DI eight output differential buffer for pcie for gen 2 14 smbus table: frequency select register, read/write address (dc/dd) pin # name control function t yp e0 1 pwd bit 7 pd_mode pd# drive mode rw driven hi-z 0 bit 6 stop_mode src_stop# drive mode rw driven hi-z 0 bit 5 pd_polarity select pd polarity rw low high 0 bit 4 reserved reserved rw x bit 3 reserved reserved rw x bit 2 pll_bw# select pll bw rw high bw low bw 1 bit 1 bypass# bypass#/pll rw fan-out zdb 1 bit 0 src_div# src divide by 2 select rw x/2 1x 1 smbus table: output control register pin # name control function t yp e0 1 pwd bit 7 dif_7 output control rw disable enable 1 bit 6 dif_6 output control rw disable enable 1 bit 5 dif_5 output control rw disable enable 1 bit 4 dif_4 output control rw disable enable 1 bit 3 dif_3 output control rw disable enable 1 bit 2 dif_2 output control rw disable enable 1 bit 1 dif_1 output control rw disable enable 1 bit 0 dif_0 output control rw disable enable 1 smbus table: output control register pin # name control function t yp e0 1 pwd bit 7 dif_7 output control rw free-run stoppable 0 bit 6 dif_6 output control rw free-run stoppable 0 bit 5 dif_5 output control rw free-run stoppable 0 bit 4 dif_4 output control rw free-run stoppable 0 bit 3 dif_3 output control rw free-run stoppable 0 bit 2 dif_2 output control rw free-run stoppable 0 bit 1 dif_1 output control rw free-run stoppable 0 bit 0 dif_0 output control rw free-run stoppable 0 smbus table: output control register pin # name control function t yp e0 1 pwd bit 7 rw x bit 6 rw x bit 5 rw x bit 4 rw x bit 3 rw x bit 2 rw x bit 1 rw x bit 0 rw x reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved 12,13 8,9 b y te 3 34,33 30,29 20,21 16,17 8,9 b y te 2 42,41 38,37 30,29 20,21 16,17 12,13 b y te 1 42,41 38,37 34,33 - - - reserved - - - reserved b y te 0 - -
idt tm /ics tm eight output differential buffer for pcie gen 2 ICS9DB803DI rev a 06/18/08 ICS9DB803DI eight output differential buffer for pcie for gen 2 15 smbus table: vendor & revision id register pin # name control function t yp e0 1 pwd bit 7 rid3 r - - x bit 6 rid2 r - - x bit 5 rid1 r - - x bit 4 rid0 r - - x bit 3 vid3 r - - 0 bit 2 vid2 r - - 0 bit 1 vid1 r - - 0 bit 0 vid0 r - - 1 smbus table: device id pin # name control function t yp e0 1 pwd bit 7 rw 0 bit 6 rw x bit 5 rw x bit 4 rw 0 bit 3 rw 0 bit 2 rw 0 bit 1 rw 1 bit 0 rw 1 smbus table: byte count register pin # name control function type 0 1 pwd bit 7 bc7 rw - - 0 bit 6 bc6 rw - - 0 bit 5 bc5 rw - - 0 bit 4 bc4 rw - - 0 bit 3 bc3 rw - - 0 bit 2 bc2 rw - - 1 bit 1 bc1 rw - - 1 bit 0 bc0 rw - - 1 device id 1 device id 6 device id 7 (msb) device id is 83 hex for 9db803 and 43 hex for 9db403 device id 5 device id 4 device id 3 device id 0 device id 2 byte 6 - writing to this register configures how many bytes will be read back. - - - - - - - b y te 5 - - - - - - - - - vendor id - - - b y te 4 - revision id - - -
idt tm /ics tm eight output differential buffer for pcie gen 2 ICS9DB803DI rev a 06/18/08 ICS9DB803DI eight output differential buffer for pcie for gen 2 16 the pd# pin cleanly shuts off all clocks and places the device into a power saving mode. pd# must be asserted before shutting off the input clock or power to insure an orderly shutdown. pd is asynchronous active-low input for both powering down the device and powering up the device. when pd# is asserted, all clocks will be driven high, or tri-stated (depending on the pd# drive mode and output control bits) before the pll is shut down. pd#, power down when pd# is sampled low by two consecutive rising edges of dif#, all dif outputs must be held high, or tri-stated (depending on the pd# drive mode and output control bits) on the next high-low transition of the dif# outputs. when the pd# drive mode bit is set to ?0?, all clock outputs will be held with dif driven high with 2 x i ref and dif# tri-stated. if the pd# drive mode bit is set to ?1?, both dif and dif# are tri-stated. pd# assertion power-up latency is less than 1 ms. this is the time from de-assertion of the pd# pin, or vdd reaching 3.3v, or the time from valid src_in clocks until the time that stable clocks are output from the device (pll locked). if the pd# drive mode bit is se t to ?1?, all the dif outputs must driven to a voltage of >200 mv within 300 us of pd# de-assertion. pd# de-assertion pwrdwn# dif dif# pwrdwn# dif dif# tstable <1ms tdrive_pwrdwn# <300us, >200mv note: polarities in timing diagrams are shown oe_inv = 0. they are similar to oe_inv = 1.
idt tm /ics tm eight output differential buffer for pcie gen 2 ICS9DB803DI rev a 06/18/08 ICS9DB803DI eight output differential buffer for pcie for gen 2 17 asserting src_stop# causes all dif outputs to stop after their next transition (if the control register settings allow the outp ut to stop). when the src_stop# drive bit is ?0?, the final state of all stopped dif outputs is dif = high and dif# = low. ther e is no change in output drive current. dif is driven with 6xi ref. dif# is not driven, but pulled low by the termination. when the src_stop# drive bit is ?1?, the final state of all dif output pins is low. both dif and dif# are not driven. src_stop# - assertion all stopped differential outputs resume normal operation in a glitch-free manner. the de-assertion latency to active outputs i s 2-6 dif clock periods, with all dif outputs resuming simultaneously. if the src_stop# drive control bit is ?1? (tri-state), al l stopped dif outputs must be driven high (>200 mv) within 10 ns of de-assertion. src_stop# - de-assertion (transition from '0' to '1') the src_stop# signal is an active-low asynchronous input that cleanly stops and starts the dif outputs. a valid clock must be present on src_in for this input to work properly. the src_stop# signal is de-bounced and must remain stable for two consecutive rising edges of dif# to be recognized as a valid assertion or de-assertion. src_stop# pwrdwn# src_stop# dif (free running) dif# (free running) dif (stoppable) dif# (stoppable) 1ms pwrdwn# src_stop# dif (free running) dif# (free running) dif (stoppable) dif# (stoppable) 1ms src_stop_1 (src_stop = driven, pd = driven) src_stop_2 (src_stop =tristate, pd = driven)
idt tm /ics tm eight output differential buffer for pcie gen 2 ICS9DB803DI rev a 06/18/08 ICS9DB803DI eight output differential buffer for pcie for gen 2 18 pwrdwn# src_stop# dif (free running) dif# (free running) dif (stoppable) dif# (stoppable) 1ms pwrdwn# src_stop# dif (free running) dif# (free running) dif (stoppable) dif# (stoppable) 1ms src_stop_4 (src_stop = tristate, pd = tristate) src_stop_3 (src_stop = driven, pd = tristate)
idt tm /ics tm eight output differential buffer for pcie gen 2 ICS9DB803DI rev a 06/18/08 ICS9DB803DI eight output differential buffer for pcie for gen 2 19 index area index area 1 2 n d h x 45 e1 e seating plane seating plane a1 a e - c - b .10 (.004) c .10 (.004) c c l min max min max a 2.41 2.80 .095 .110 a1 0.20 0.40 .008 .016 b 0.20 0.34 .008 .0135 c 0.13 0.25 .005 .010 d e 10.03 10.68 .395 .420 e1 7.40 7.60 .291 .299 e h 0.38 0.64 .015 .025 l 0.50 1.02 .020 .040 n 0 8 0 8 min max min max 48 15.75 16.00 .620 .630 10-0034 symbol in millimeters in inches common dimensions common dimensions see variations see variations 0.635 basic 0.025 basic reference doc.: jedec publication 95, mo-118 variations see variations see variations n d mm. d (inch) ordering information ics9db803dfilft example: designation for tape and reel packaging lead free, rohs compliant industrial temperature package type f = ssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx d f i lf t
idt tm /ics tm eight output differential buffer for pcie gen 2 ICS9DB803DI rev a 06/18/08 ICS9DB803DI eight output differential buffer for pcie for gen 2 20 index area index area 12 1 2 n d e1 e seating plane seating plane a1 a a2 e -c- - c - b c l aaa c min max min max a -- 1.20 -- .047 a1 0.05 0.15 .002 .006 a2 0.80 1.05 .032 .041 b 0.17 0.27 .007 .011 c 0.09 0.20 .0035 .008 d e e1 6.00 6.20 .236 .244 e l 0.45 0.75 .018 .030 n a 0808 aaa -- 0.10 -- .004 variations min max min max 48 12.40 12.60 .488 .496 10-0039 reference doc.: jedec publication 95, mo-153 in millimeters in inches common dimensions 0.50 basic 0.020 basic 8.10 basic 0.319 basic n d (inch) see variations see variations d mm. 48-lead, 6.10 mm. body, 0.50 mm. pitch tssop (240 mil) (20 mil) symbol see variations common dimensions see variations ordering information ics9db803dgilft example: designation for tape and reel packaging lead free, rohs compliant industrial temperature package type g = tssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx d g i lf t
ICS9DB803DI eight output differential buffer for pcie gen 2 21 innovate with idt and accelerate your future networks. contact: www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support 408-284-6578 pcclockhelp@idt.com corporate headquarters integrated device technology, inc. 6024 silver creek valley road san jose, ca 95138 united states 800 345 7015 +408 284 8200 (outside u.s.) asia pacific and japan integrated device technology singapore (1997) pte. ltd. reg. no. 199707558g 435 orchard road #20-03 wisma atria singapore 238877 +65 6 887 5505 europe idt europe, limited prime house barnett wood lane leatherhead, surrey united kingdom kt22 7de +44 1372 363 339 ? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa tm revision history rev. issue date description page # 0.1 6/18/2008 1. initial release a

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